Processor-based systems, such as computer systems, use memory devices, such as dynamic random access memory (“DRAM”) devices, to store instructions and data that are accessed by a processor. These memory devices are typically used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data is transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.
One approach to alleviating the limited data bandwidth and memory latency problems is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory hub controller is coupled to several memory modules, each of which includes a memory hub coupled to several memory devices. The system controller or memory hub controller is coupled to the memory module via a high-speed bus or link over which signals, such as command, address, or data signals, are transferred at a very high rate.
The very high rate at which command, address and write data signals are coupled to such memory modules and the very high rate at which read data signals are coupled from such memory modules make it difficult to test such memory modules at their normal operating speed. In particular, memory test systems are not generally available that are capable of operating at the normal operating speed of such devices.
One approach that has been used to test memory modules having a memory hub coupled to several memory devices is to include built-in test circuitry in the memory hub. However, this approach can unduly increase the cost of such memory modules, and the ease at which they may be re-configured to alter the manner in which tests are performed may be severely limited. Current methods do not test all functionality of the memory modules but instead normally test a limited range of the functions performed by the memory modules.
There is therefore a need for a method and system that allows memory modules having a memory hub coupled to several memory devices to be tested in the native mode that it will ultimately be used in its end application. This includes speed of operation as well as logical interface.